The chip is controlled using an SPI bus consisting of six signals. For any engineers unfamiliar, don't worry, the heart of an SPI
system only requires three signals given it is simply a shift register arrangement, extending to the outside world (a) the output
from the last stage of the register, (b) the input to the first stage and (c) the clock. As the clock runs, whatever had been written
in parallel to the shift register, will be serially output on the output pin, while whatever data is presented on the input pin
will be shifted into the register at the same time. So n clock pulses later, the output will have sent n bits while n bits (presented
on the input) will be sitting ready to read from the shift register. PIC32MX chips usually build in 1 to 4 SPI interfaces and allow
variable width SPI (8, 16 or 32 bit) - but for the NRF24L01 32 bit SPI transfers are required.
Three other strobes are required... two are outputs from the controlling CPU (inputs to the NRF24L01) and one is an output from the NRF24L01.
The first of these is an active low chip select signal (called CSN) which is asserted by the controlling CPU whenever the SPI is being used
to read or write data to/from the NRF24L01. The 2nd signal called CE (chip enable) is active high and is used to switch on the transmission
/ reception sections of the chip. The third and last signal is an output from the NRF24L01 and is used to raise interrupts in the controlling
CPU. This signal asserts after data has been transmitted, received or when the maximum number of retries have been exceeded... yep, you read
that right. This little chip has a protocol built in that demands an acknowledgement packet after a transmission and it will retry up to 15
times, with a configurable delay between retries if that ACK isn't received..